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-- Company: 
-- Engineer: 
-- 
-- Create Date:    17:32:39 12/01/2009 
-- Design Name: 
-- Module Name:    Mux - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Mux is
    Port ( In1 : in  STD_LOGIC_VECTOR (15 downto 0);
           In2 : in  STD_LOGIC_VECTOR (15 downto 0);
           --In3 : in  STD_LOGIC_VECTOR (15 downto 0);
           --In4 : in  STD_LOGIC_VECTOR (15 downto 0);
           --Ctrl : in  STD_LOGIC_VECTOR (1 downto 0);
			  Ctrl : in  STD_LOGIC ;
           Out1 : out  STD_LOGIC_VECTOR (15 downto 0));
end Mux;

architecture Behavioral of Mux is
				
begin
		sel_input : process is
		
		begin
			if	Ctrl then
					Out1 <= In1;
			else
					Out1 <= In2;
			end if;
		end process sel_input;

end Behavioral;

